1. Field of the Invention
The invention relates to a method and device for signal synchronization, and in particular, to a method of adjusting a dummy period to make a receiving device to receive data from an output device synchronously.
2. Description of the Related Art
Currently, phase locked loops (PLLs) remain a core of clock generators. A clock generator generates clocks of different frequencies by phase locked loops (PLLs), receiving the same base frequency provided by a crystal, associated with different frequency dividers such that multiple crystal oscillators in a conventional system are replaced.
A phase locked loop (PLL) has two input terminals respectively receiving a reference frequency Fref and a feedback frequency Fvco and an output terminal receiving an output frequency Fout. The relationship between the frequencies is expressed as Fout=(Fref×P)/(Q×N).
A phase locked loop (PLL), a negative feedback system, comprises a feedback signal in the loop utilized to lock frequency and phase of an output signal to the reference signal on the input terminal. A phase frequency detector (PFD) compares frequencies and phases of the reference frequency Fref and the feedback frequency Fvco and detects differences therebetween such that output frequency of a voltage controlled oscillator (VCO) is controlled thereby. When Fref/Q exceeds Fvco/P, a high voltage output UP increases the output frequency Fout. Conversely, when Fref/Q is lower than Fvco/P, a high voltage output DN reduces the output frequency Fout. As a result, a stable output state as shown by the formula is eventually achieved. Accordingly, P, Q, and R of the frequency dividers of the PLL are adjusted such that a required frequency is obtained.
Generally, clocks of devices in a system are generated by the aforementioned PLL. The clocks generated by the PLL, however, generate considerable noise. The devices in the system may receive the clock signal provided by the PLL. While ideally, the devices receive the same clock signal, there is a slight difference. As a result, a receiving device cannot receive data output from an output device during data transmission.
FIG. 1 is a block diagram of a conventional image system. In FIG. 1, the image system 100 comprises image decoder 101 and digital signal processor 103. Image decoder 101 and digital signal decoder 103 respectively receive clock signals Clock 1 and Clock 2. When data 105 is transmitted from image decoder 101 to digital signal processor 103, digital signal processor 103 may not be synchronized with the data 105 from the image decoder due to different clock signals Clock 1 and Clock 2.
The invention provides a method and a signal synchronization device wherein a receiving device can be synchronized with data from an output device even when clock signals thereof are skewed.